The present invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a semiconductor device fabricating method wherein an interlayer insulation film is formed on a diffusion region between gate electrodes which constitute a MOS (metal oxide semiconductor) transistor and a contact hole is formed in the interlayer insulation film in self-aligned relation to the gate electrodes.
Hitherto, there has been known a method as defined by the steps shown in FIGS. 4A through 4G for forming a contact hole on a source or drain region between gate electrodes constituting a MOS transistor in self-aligned relation to the gate electrodes. It is noted that in this example the MOS transistor is an N-channel type MOS transistor having an LDD (lightly doped drain) structure.
As FIG. 4A shows, on a p-type silicon substrate (in an active region thereof) 41 having an isolation region (not shown) formed therein by LOCOS (local oxidation) technique, for example, is first formed a film of silicon oxide 42 as a gate insulating film by thermal oxidation, and a polycrystal silicon film 43 and a tungsten silicide film 44 which are to be used as gate electrode materials are sequentially deposited by a CVD (chemical vapor deposition) method over the silicon oxide 42, then a silicon oxide film 45 is formed over the tungsten silicide 44 by the CVD method.
Subsequently, a photolithographic step is carried out to provide a resist (not shown) in a region to be formed into a gate of the MOS transistor, and reactive ion etching is carried out using the resist as a mask to remove silicon oxide 45, tungsten silicide 44, and polycrystal silicon 43. As a result, gate electrodes G comprised of tungsten silicide 44 and polycrystal silicon 43 are formed as such. After removal of the resist, ion implantation is carried out utilizing the silicon oxide 45 and gate electrodes G as masks to form an N-type low-density diffusion layer 46 which is to act as an LDD region.
Next, after a silicon oxide film 47 is deposited over the entire surface as shown in FIG. 4B, anisotropic etching back is carried out to form a side wall film comprised of a silicon oxide film 47 on both sides of silicon oxide film 45 and gate electrode G as shown in FIG. 4C. Then, ion implantation is carried out using the side wall film 47, silicon oxide 45, and gate electrodes G as masks to form an N-type high density diffusion layer 48 which is to act as a source or drain region (LDD structure).
Next, as FIG. 4D shows, a silicon nitride film 49 and a silicon oxide film 50 are sequentially deposited on the entire surface as interlayer insulation films for electrically isolating the gate electrodes G from an overlying wiring arrangement not shown. The silicon oxide 50 is deposited comparatively thick so that it may have a planar surface configuration. Generally, such flat surface formation of the interlayer insulation films is required for the purpose of facilitating the patterning of the overlying wiring arrangement. The reason why the silicon nitride film 49 is deposited prior to the deposition of the silicon oxide film 50 is that if the silicon oxide film 50 only is deposited, there is a fear that at a later stage of contact hole opening, the silicon oxide 45 may also be etched so that the gate electrode G is exposed. Therefore, the silicon nitride 49, as insulating material which can be selectively etched relative to the silicon oxide, is deposited as stated above before the silicon oxide 50 is deposited as such.
Next, as FIG. 4E shows, a photolithographic operation is carried out to form a resist R having an opening 51 on the silicon oxide film 50 for use as a mask for forming a contact hole. The size of the opening 51 of the resist R (dimensions within planes parallel to the substrate) contains opposed side walls 47, 47 of adjacent gate electrodes G, G and also contains part of the gate electrodes G by way of allowance. Subsequently, etching is carried out using the resist R as a mask to remove silicon oxide 50 selectively relative to the silicon nitride film 49, that is, under such conditions as will make the silicon nitride 49 not liable to be etched. As a result, a portion H.sub.1 of a contact hole is formed. In this case, etching stops on the surface of the silicon nitride film 49.
Then, as FIG. 4F shows, the silicon nitride 49 exposed within the opening 51 of the resist R is selectively etched off in relation to the silicon oxide. In this case, side wall films 49a, 49a composed of silicon nitride remain unremoved on opposed sides of the side wall films 47, 47. If an attempt is made to remove such side wall film 49a, the time period of etching is prolonged and this may cause damage to the silicon substrate. Therefore, the time period of etching is set to a time period of the order of slightly more than the time required in etching off the silicon nitride 49 throughout its deposited thickness.
Next, as FIG. 4G shows, the silicon oxide film 42 remaining on a source/drain region between the opposed side wall films 49a, 49a is etched off. In this way, a lower portion H.sub.2 of contact hole H is formed in a self-aligned manner between the opposed side wall films 49a, 49a, whereby the contact hole H is formed which extends from the surface side of the interlayer insulation film 50 to the surface of the source/drain region 48.
However, according to this fabricating method, the lower portion H.sub.2 of contact hole H is formed in a region corresponding to the space between the opposed side wall films 49a, 49a. Therefore, in order to secure necessary area for the contact hole H.sub.2, it is necessary that the distance between adjacent gate electrodes G, G be preset relatively large, at the stage of pattern designing, allowing for the thickness (shown widthwise) of side wall films 49a, 49a in addition to the thickness (shown widthwise) of the side wall films 47, 47. This poses a problem that where a semiconductor integrated circuit having a plurality of such MOS transistors arranged on a semiconductor substrate is to be constructed, micro-fine patterning is hindered.
Where the MOS transistor is a non-volatile memory transistor having a floating gate, there is known a fabricating method as illustrated in FIGS. 5A through 5F.
First, as FIG. 5A shows, on a p-type silicon substrate (in an active region thereof) 61 having an isolation region (not shown) formed therein by LOCOS (local oxidation) technique, for example, is formed a silicon oxide film 62 as a first gate insulating film by thermal oxidation, and a film of polycrystal silicon 63 to be used as material for floating gate electrodes is deposited over the silicon oxide film 62. Then, a photolithographic step is carried out to provide a resist (not shown) in a region to be formed into a floating gate, and reactive ion etching is carried out using the resist as a mask to remove polycrystal silicon 63. It is noted that at this stage the remaining polycrystal silicon 63 occupies a larger area than shown.
Thereafter, on the remaining polycrystal silicon film 63 is formed an ONO film (a three-layer film consisting of silicon oxide film/silicon nitride film/silicon oxide film) 64 which is to serve as a second gate insulating film, and then a polycrystal silicon film 65 and a tungsten silicide film 66 which are to be used as material of a control gate electrode are sequentially deposited by the CVD technique over the ONO film (it is to be noted in this connection that in some case a silicon oxide film may be deposited over the tungsten silicide 66).
Subsequently, a photolithographic step is carried out to provide a resist (not shown) in a region to be formed into a control gate, and reactive ion etching is carried out using the resist as a mask to sequentially etch off tungsten silicide 66, polycrystal silicon 65. ONO film 64, and polycrystal silicon 63. As a result, a control gate electrode CG and a floating gate electrode FG are formed in same region.
Then, after removal of the resist, ion implantation is carried out using the control electrode CG, etc. as masks thereby to form an N-type high density diffusion layer 67 which is to be formed into a source or drain region.
Next, as FIG. 5B shows, thermal oxidation is carried out in an oxygen atmosphere to form a silicon oxide film 68a on sides of the polycrystal silicon film 63 which constitutes a floating gate electrode FG, the silicon oxide film 68a having comparatively good electric insulation characteristic. The reason for forming the silicon oxide film 68a is that in a non-volatile memory transistor having a floating gate, wherein the state of the memory transistor as a memory element in writing and erasing is defined by the quantity of charge accumulated in the floating gate electrode FG, it is necessary to improve the insulating characteristic of the floating gate electrode FG. It is noted in the above connection that simultaneously with the formation of the silicon oxide film 68a on sides of the floating gate electrode FG are formed a silicon oxide film 68b on sides of the polycrystal silicon 65 which is a constituent of the control gate electrode CG, and silicon oxide films 68c and 68d respectively on sides and top of the tungsten silicide 66. The surface side of the source/drain region 67 is oxidated and a silicon oxide film 68e is formed thereon in place of the first gate insulating film 62. For example, where the thickness d1 of the silicon oxide film 68a is set to 50 nm for enabling the floating gate electrode FG to have good insulating property, the thickness d2 of the silicon oxide film 68b is 50 nm, the thickness d3, d4 of the silicon oxide films 68c, 68d is 80 nm, and the thickness d5 of the silicon oxide film 68e is 100 nm. The reason for d1&lt;d5 is that the quantity of impurities injected into the source/drain region 67 is larger than the quantity of impurities injected into the floating gate electrode FG. When the polycrystal silicon film is oxidated, the position of the film surface (an interface relative to the silicon oxide film) is changed, whereas no changes occur in the surface position when the tungsten silicide is oxidated. Therefore, the upper portion 66 of the control gate electrode CG is larger in width than the lower portion 65 thereof. Furthermore, the thickness d3 of the silicon oxide film 68c is larger than the thickness d1, d2 of the silicon oxide films 68a, 68b. Therefore, the silicon oxide films 68a, 68b, 68c have an overhang configuration.
Next, as FIG. 5C shows, a silicon nitride film 69 and a silicon oxide film 70 are sequentially deposited on the entire surface as interlayer insulation films for electrically isolating the gate electrodes G from the overlying wiring arrangement not shown. The silicon oxide film 70 is deposited comparatively thick so that it may have a planar surface configuration. The silicon nitride film 69 is deposited as insulating material which can be selectively etched relative to the silicon oxide.
Next, as FIG. 5D shows, a photolithographic operation is carried out to form a resist R having an opening 71 on the silicon oxide film 70 for use as a mask for forming a contact hole. Then, etching is carried out using the resist R as a mask to remove silicon oxide film 70 selectively relative to the silicon nitride 69, that is, under such conditions as will make the silicon nitride 69 not liable to be etched. As a result, a portion H.sub.1 of a contact hole is formed. In this case, etching stops on the surface of the silicon nitride film 69. However, a portion 70a of the silicon oxide film 70 remains unremoved under a shade (recess) produced in the silicon nitride film 69 due to the overhang configuration of the silicon oxide films 68a, 68b, 68c.
Then, as FIG. 5E shows, the silicon nitride film 69 exposed within the opening 71 of the resist R is selectively etched off in relation to the silicon oxide film. In this case, a side wall film 69a composed of silicon nitride remains unremoved between the silicon oxide film 68 (and ONO film 64) and the portion 70a of silicon oxide.
Next, as FIG. 5F shows, the silicon oxide film 68 remaining on a source/drain region between the opposed side wall films 69a, 69a is etched off. In this way, a lower portion H.sub.2 of contact hole H is formed in a self-aligned manner between the opposed side wall films 69a, 69a, whereby a contact hole H is formed which extends from the surface side of the interlayer insulation film 70 to the surface of the source/drain region 67.
However, according to this fabricating method, as is the case with the fabrication of a MOS transistor having an LDD structure, the lower portion H.sub.2 of contact hole H is formed in the space between the opposed side wall films 69a, 69a. Therefore, in order to secure necessary area for the contact hole H.sub.2, it is necessary that the distance between adjacent control gate electrodes CG and CG be preset relatively large, at the stage of pattern designing, allowing for the thickness (shown widthwise) of side wall films 69a, 69a in addition to the thickness of the silicon oxide film 68. This poses a problem that where a semiconductor integrated circuit having a plurality of such non-volatile memory transistors arranged on a semiconductor substrate is to be constructed, micro-fine patterning is hindered. Another problem is that at the stage of forming the lower portion H.sub.2 of the contact hole H, that is, at the time of etching off the silicon oxide film 68e (of thickness d5) on the source/drain region 67, the silicon oxide film 68c (of thickness d3&lt;d5) covering the side of the tungsten silicide film 66 is also partly etched off. As a result, the tungsten silicide film 66 is exposed within the contact hole H, and this involves the danger of short-circuiting between the overlying wiring and the control gate electrode CG.